The recent surge in interest in multichip modules (MCMs) is a natural extension of the computer industries' relentless pursuit of high speed computing, with minimal size/weight/power requirements, at a reasonable cost. Such modules allow already highly integrated chips to be closely spaced and yet interact via wide data buses (with high input/output (I/O)), both of which dramatically improve device performance.
For all their advantages, MCMs pose a major testing challenge. Many MCMs can contain over one million transistors, each of which should be tested. Worse yet, test methods traditionally used at the card/board level, where chip leads can be probed directly, are not applicable to MCMs. This can mean an incompletely tested product or excessive test-related costs.
Testing already represents a substantial portion of overall product cost, perhaps as high as fifty (50%) percent. This cost consists of the expense associated with developing the test, and the recurring cost of applying the test to manufactured product. The alternative, reducing present expense by spending less effort to develop an effective test, actually ultimately raises product cost as defective electrical components then slip through undetected and must be weeded out by a board, unit or system test or, even worse, in the field. In general, the higher the level of packaging, the more expensive the cost of diagnosis and repair. Experts have estimated that this cost may increase by a factor of 10.times. for each level of packaging. This is most likely a conservative estimate, which means that detecting a defective MCM at the unit or system level could be 100 or 1000 times more expensive that detecting the defect immediately during MCM manufacturing. Thus, enhancing MCM testing can be considered critical to profitability of a multichip module manufacturer.
Testing of MCMs is further complicated by the trend towards diversification within the semiconductor computer industry. Specifically, in contrast to prior MCM fabrication facilities in which the integrated circuit chips and MCMs were both designed and tested by the same company, an MCM foundry is today supplied tested chips ("die") and has the sole task of mounting these die on an MCM substrate. In such an environment, the foundry most likely does not have access to the details of the internal circuitry within the supplied die. Thus, a major dilemma is often presented for manufacturing testing.
In addition to any one of the one million or so transistors which may be defective, the MCM mounting process cannot guarantee 100 percent effectiveness, and thus must be verified via testing. Testing must be rigorous, since today's customers demand extremely high quality levels, as measured in number of defective packages per million shipped. Such high quality testing is difficult enough when the chips and MCM are both designed by the same facility, but can be extremely problematic when the chips are designed and fabricated by a semiconductor facility that may consider the design and test patterns to be proprietary.
Currently, two major approaches to solving the problem of testing MCMs have been employed. First, metal pads have been placed on a top surface of an MCM's substrate, surrounding each chip site. Wiring within the carrier substrate provides electrical connection between these pads and the I/O of each integrated circuit chip mounted on the substrate. This technique, similar to in-circuit-testing used at the card and board level of packaging, allows the test(s) applied during wafer fabrication to be reapplied at the MCM level of packaging. Unfortunately, there are several disadvantages to this approach.
First, space must be provided for the pads on a top surface of the MCM substrate, increasing significantly the total size of the MCM. This not only impacts the area taken by the package, but also increases the distance between chips of the MCM, thereby reducing MCM performance. Obviously, close chip spacing is a major objective/advantage to MCMs. Secondly, reliable probing of the mounted chips, and providing cooling for heat generated during testing, are sufficiently difficult that the equipment to perform such testing can cost millions of dollars. Finally, a major portion of defects at the MCM fabrication level can comprise inoperative substrate interconnect circuitry, which cannot be tested using this probing technique.
A second approach to MCM testing is to alter each integrated circuit chip to provide the logical equivalent of the above-discussed chip isolate probing. The most popular embodiment of this approach is described by IEEE Standard 1149.1 (see, e.g., Maunder et al., entitled "The Test Access Port and Boundary-Scan Architecture," IEEE Computer Society of Press Tutorial, ch. 4, pp. 33-49 (1990)). In this standard, referred to as boundary-scan, latches are provided at each integrated circuit chip I/O to allow the chip to be independently tested by shifting data into the chip input latches, clocking the chip, and then shifting data out from the chip output latches to determine states propagated through the chip. In contrast to the probing method, substrate interconnections can be tested by shifting data into the latches at a given chip's outputs, performing a chip-to-chip data transfer, and then shifting out the contents of the output latches of the chip fed by the driving chip to ensure that proper electrical continuity exists between the chips.
Boundary-scan is an effective solution to the MCM testing problem where the integrated circuit chips are designed to accommodate such testing. However, many of today's integrated circuit chips do not conform to the standard since the chips were not intended for MCM applications, or were designed prior to the introduction of the IEEE standard. Thus, this invention addresses the broad class of MCMs designed with integrated circuit chips that do not conform to the boundary-scan standard.